This is still a very challenging task. “Packaging is not as easy as saying, ‘I want to run 100,000 wafers per month,'” Jim McGregor, founder and long-time analyst of the chip industry, Tirias Research, describes a steady flow of semiconductors in different stages of manufacture. “It really comes down to whether Intel’s [packaging] fabs can make deals. If we see them expanding those operations more, that’s an indicator that they have.”
Anwar Ibrahim, Malaysia’s prime minister, announced in a Facebook post last month that Intel will expand its Malaysian chips-making facility, established in 1970. Ibrahim stated that Naga Chandrasekaran was the Foundry head at Intel. “outlined plans to commence the first phase” The expansion would involve advanced packaging.
“I welcome Intel’s decision to begin operations for the complex later this year,” “A translated version” of Ibrahim’s message read. John Hipsher from Intel confirmed the expansion of chip assembly and testing capacity in Penang. “amid rising global demand for Intel Foundry packaging solutions.”
Purchase Packages
Chandrasekaran is the man who spoke to WIRED exclusively during this report and took charge of Intel’s Foundry in 2025. “advanced packaging” It was not even a thing ten years ago.
The integration of capacitors and transistors to control and store power has always been a requirement for chips. The semiconductor industry focused for a very long time on shrinking components. In the decade of 2010, as the demand for computers increased, chip manufacturers began to pack in more processing units, memory with high bandwidth, and other necessary components. In order to maximize power and memory, chipmakers eventually began using a “system-in-packages” or ‘package-on-package’ approach. This involved stacking multiple components onto one another. 2D stacking became 3D.
TSMC is the leading semiconductor company in the world. TSMC started offering customers CoWoS packaging (chip-on-wafer-on substrate) technology and later SoIC (systems on integrated chips) technologies. Essentially, the pitch was that TSMC would handle not just the front end of chip-making—the wafer part—but also the back end, where all of the chip tech would be packaged together.
Intel had ceded to TSMC its lead in the chip industry at this time, but it continued to invest heavily into packaging. It launched EMIB in 2017, or the embedded multi-die Interconnect Bridge, that was unique, because it reduced the physical connections or bridges between the various components of the chip package. Foveros was launched in 2019 as an improved die-stacking method. The next step in packaging innovation was a larger leap for the company: EMIB T.
EMIB T, announced last May by Intel, promises to increase power efficiency as well as signal integrity among all components. Former Intel employees with first-hand knowledge of Intel’s packaging initiatives tell WIRED Intel’s EMIB/EMIB T are intended to provide a better signal integrity between all the components on the chip. “surgical” TSMC uses a more efficient way of packing chips. This is a chip that’s supposed to save power, space and, ideally save the customer money over time. The company claims EMIB will be rolled out this year in fabs.
